360 DV & 360 EC

High value, differentiated products and highly focused formal apps

OneSpin provides 2 major product lines, OneSpin 360 DV and OneSpin 360 EC. In addition specializations for unique application spaces and 3rd party extensions are available.

 

The Solution Platform

Each solution is built upon a series of precisely targeted apps, facilitating specific methodologies. These apps have been conditioned to work within the solution set, naturally fitting to specific needs and use models. At the center of the OneSpin solutions is a state-of-the art formal platform. Using this approach, verification efficiency can be transformed without painful learning curves and operational drudgery.



360 DV-Inspect Features:

  • Automatic Code Inspections
  • Structural Analysis
  • Safety Check
  • Activation Checks

360 DV-Verify Features:

  • Quantify Observation Coverage
  • Register Checks
  • Scoreboarding
  • Connectivity Checking
  • Protocol Compliance
  • X-Propagation Analysis
  • Operational SVA

360 DV-Certify Features:

  • Automates the analysis of sets of Operational SVA, detecting inconsistencies, errors, and gaps in both verification plans and specifications
  • An intuitive debug environment enables engineers to pinpoint shortcomings and guides them on how to systematically improve their sets of assertions

360 EC-FPGA Features:

  • Ensures that complex FPGAs are free of synthesis and optimization errors
  • Dramatically accelerates the design implementation and debug loop
  • Allows risk-free use of advanced synthesis optimization
  • Eliminates gate level simulation and stimulus, easy to setup and apply
  • Supports all FPGA synthesis optimizations, including complex sequential retiming

360 EC-ASIC Features:

  • Requires no change to the design team's existing design flow
  • Significantly eases chip level simulation by ensuring equivalence between implementation levels
  • Deploys multi-threaded proof engines
  • Verifies multimillion gate designs
  • Handles large multipliers, operator merging and resource sharing with datapath analysis capability
  • Supports low-power implementations and clock gating
  • Focuses debug with logic cone extraction and highlighting
  • Avoids false negatives associated with library cells by qualifying cell libraries with sequential checking
  • Supported design languages: Verilog, SystemVerilog, VHDL, EDIF, Liberty and mixed languages
  • Supported computer platforms: Linux, Solaris