A powerful ECO tool to patch the synthesised netlist according to the new specification

Easy-logic who is specialized in developing electronic design automation (EDA) tools for high-end integrated circuit (IC) designs supplies the unique ECO technology (EasyECO). If it need manually ECO to modify may need larger patch and increase the difficulty of time closure. Today’s AI and IoT chips have triggered a fundamental architectural change: the arithmetic components suddenly jumped to 50%~80% of the entire chip resource due to greater computing requirements. ECO operation is guided by a patented Reverse Engineering (like an "endoscopy") technique to locate the exact spot of the ECO changes. We have also removed the conventional constraints of "adding patches only" for the best chance of achieving a minimum timing impact. The direct result is to help the follow-up Timing Closure much easier and to produce a more market competitive and highest quality chip!

Five Simple Reasons for you to consider Easy ECO

  • Manual ECO may miss a good patch, Easy ECO would have better performance
    (Why? The original RTL corresponded signals g3, g5 have been deleted in the DC-synthesized netlist (c). It is already unlikely for engineers to do internal manual correction any more. )

  • “If -then-else“ external patching may cause Timing Closure problems
    A common practice for fixing a commercial software bug is to add an external "if-then-else" patch like: If (bug xxx happens) then {do yyyy(); go back to previous codes; }, which may turn an one line code changeinto a 10s or even 100s lines of external patch code addition. Unfortunately, a MUX based "if-then-else" External ECO patching is not unusual in IC designs ECOed manually. This ECO practice may bring a tougher challenge to the follow-up Timing Closure process.

  • The closer the better (To stop a finger cut bleeding, should we tie a rubber band at the finger or a tourniquet at the upper arm)
    It is obviously understandable that the closer the patching is to the problem spot, the smaller a patch could be. However, especially in a flattened huge arithmetic circuit netlist, it is very difficult to locate the exact spots for doing a right internal ECO operation. A complete understanding on the functionality of every line and gate is demanded in our Reverse Engineering developed for carrying out this job.

  • Lifting the constraint of the adding Patch only for the Best Chance of Excellent Timing
    In view of this, we have integrated a very powerful Rewiring technique (that our group has over 20 years of accumulated R&D experience) for doing the ECO operations. Our Rewiring is designed to do logic transformations with minimum perturbation on the original logic and with gate increase as minimal as possible. (A larger patch might require more connections to spare cells at remote locations in Metal ECO, which might cause a much larger delay.)

  • 50% to 90% chip resources are arithmetic
    In the coming AI+IoT era, more and more chips are designed with higher and higher parallel arithmetic computing power. Our 3rd gen DSP ECO can probably fit best for their ECO requests demanding the highest timing performance.

Performance of Easy Functional/Metal ECO of Clients' Cases