STAR is a RTL design solution which helps in design exploration, editing and structure verification. Based on set of EDA tools that work seamlessly together, build a complete solution to shorten the path towards a ready for synthesis RTL code. Through its unique “Build&Signoff” design capabilities, STAR offers to designers, in one script, the ability to extract design information, edit and generate the synthesizable RTL code and finally signoff the resulting RTL code. The “Build&Signoff solution is providing the following EDA tools:

• STAR RTL Design Builder : Design Building and RTL Editing with Generation of Synthesizable RTL

• STAR RTL Design Checker :RTL Design Exploration and Simulation-Free Structural Verification

• STAR RTL IP Integration : Easy IP Packaging, Integration and Reuse

• STAR Padring : Graphical PADring Placement with RTL Generation

• STAR RTL low Power : Power Intent Exploration with Design Compliance

• STAR RTL DFT : Testability Evaluation, Debug & Enhancement at RTL

Typical RTL Design Solution features are:

• Offer flexibility, in-depth design exploration and debug through Tcl interface : query design objects, extract fanin / fanout cone, extract hierarchical paths, etc.

• Complete set of commands for incremental editing during the same run :add / remove instance, nets, ports, create / modify connections, change instance references, rename designs etc.

• GUI debug environment cross link : probing RTL / Schematic and coherency RTL / Gate level netlist